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MITSUBISHI DIGITAL ASSP MITSUBISHI DIGITAL ASSP
M66238FP M66238FP
STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
DESCRIPTION The M66238 is a LSI that incorporates a PLL synthesizer and a sync clock generator in it. The PLL synthesizer covers the range of 25MHz to 50MHz at the minimum steps of 3kHz. The sync circuit outputs a clock and a one-shot pulse which are synchronized with an external trigger signal. Setting a dividing ratio allows acquisition of sync clock outputs within the range of 0.78MHz to 25MHz. FEATURES * Sync clock output frequency range: 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 of 25 to 50MHz * Sync accuracy (jitter): 3ns * Trigger input: Polarity selectable * One-shot pulse output: Polarity and width selectable * 5V power supply APPLICATION Pixel clock generator
PIN CONFIGURATION (TOP VIEW)
DIGITAL GND PIN DGND
1
32 31 30
RESET INPUT RESET 2
CHIP SELECT INPUT
SERIAL DATA INPUT
CS 3 SIN 4
AGND ANALOG GND PIN ANALOG POWER AVCC SUPPLY PIN AGND ANALOG GND PIN
29 RV 28 27
SERIAL CLOCK INPUT SCLK 5 CLOCK OUTPUT XOUT 6 CLOCK INPUT
VCO LOAD OUTPUT ANALOG POWER AVCC SUPPLY PIN AGND ANALOG GND PIN FILTER CONNECT PIN
AGND ANALOG GND PIN
XIN 7 8
26 CPIN 25
M66238FP
DIGITAL GND PIN DGND
DIGITAL POWER DVCC 9 SUPPLY PIN 10 TCKI TEST PIN TCKO 11 PLL OUTPUT CKO/PLLO 12 CLOCK OUTPUT CKOB 13
ONE-SHOT PULSE OUTPUT PULSE 14
24 CPOUT FILTER CONNECT PIN 23 22 21 20 19 18
DGND DIGITAL GND PIN DVCC DIGITAL POWER SUPPLY PIN UP TEST PIN DOWN DIGITAL POWER DVCC SUPPLY PIN DGND DIGITAL GND PIN
SYNC OUTPUT POWER SUPPLY PIN VCCO SYNC OUTPUT GND PIN GNDO
15 16
17 TR
TRIGGER INPUT
Outline 32P2W-A
BLOCK DIAGRAM
CHIP SELECT INPUT SERIAL DATA INPUT SERIAL CLOCK INPUT
CS 3 SIN 4 SCLK 5
SERIAL WRITE CONTROL CIRCUIT
COMMAND REGISTER
COMMAND CONTROL CIRCUIT
10 TCKI TEST PIN 11 TCKO
15 12
CLOCK INPUT CLOCK OUTPUT
XIN 7 XOUT 6
CRYSTAL OSCILLATOR CIRCUIT fin
15-BIT COUNTER
12-BIT DIVIDER
PHASE COMPARATOR
VCO 25MHz ~ 50MHz
fvco SYNC/DIVIDER CIRCUIT SYNC CLOCK GENERATOR 12 CKO/PLLO PLL OUTPUT 13 CKOB 14 PULSE CLOCK OUTPUT ONE-SHOT PULSE OUTPUT
RESET INPUT RESET 2
CHARGE PUMP
(
)
TRIGGER INPUT
TR 17
21 UP
20
24
26 CPIN
29 RV
DOWN CPOUT TEST PIN
FILTER CONNECT PIN VCO LOAD OUTPUT
FILTER CONNECT PIN
1
MITSUBISHI DIGITAL ASSP
M66238FP
STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
PIN DESCRIPTIONS
Pin name RESET CS SIN SCLK XIN XOUT TR CKOB Name Reset input Chip select input Serial data input Serial clock input Clock input Clock output Trigger input Clock output I/O Input Input Input Input Input Output Input Output Output Output Output Input Output Input Output Output Output -- -- -- -- -- -- Function Initialize M66238 internal status. Transfer serial data when CS="L". Synchronize 32-bit serial data from MCU with SCK, and enter. Enter a sync clock for writing 32-bit serial data. Used by connecting crystal oscillator between XIN and XOUT. When using an external clock signal, connect the clock oscillator to XIN pin and open XOUT pin. Trigger input for clock sync. Output an inverted CKO signal. CKO outputs a clock synchronized with a trigger signal and PLLO outputs a PLL oscillator clock as it is. Output a one-shot pulse synchronized with a CKO signal. Connect a low pass filter to charge pump output. Low pass filter input pin. Connect a load resistor for VCO circuit operation between RV and GND. Shipping test pin. Connect to GND when use. Shipping test pin. Keep open when use. Shipping test pin. Keep open when use. Shipping test pin. Keep open when use. Digital power supply pin. Digital GND pin. Power supply pin for sync output. GND pin for sync output. Analog power supply pin. Analog GND pin.
CKO/PLLO PLL output PULSE CPOUT CPIN RV TCKI TCKO UP DOWN DVCC DGND VCCO GNDO AVCC AGND One-shot pulse output Filter connect pin Filter connect pin VCO load output Test pin Test pin Test pin Test pin Digital power supply pin Digital GND pin Sync output power supply pin Sync output GND pin Analog power supply pin Analog GND pin
LIST OF REGISTER SETTING COMMANDS
A1 0 A0 0 Setting Setting of CKO/PLLO dividing ratio, PLL synthesizer 15-bit generation dividing ratio and reference clock generation 12-bit dividing ratio. Setting of one-shot pulse polarity and width, setting of trigger edge, HALT of entire M66238, HALT of charge pump and VCO, phase comparator output UP/DOWN, CKO/PLLO switching. Dummy trigger generation command
1
0
1
1
SERIAL DATA WRITE TIMING
CS
SCLK
SIN
A0
A1
D0
D1
D2
D3
D4
D5
D6
D26
D27
D28
D29
Address bit
Data bit
2
MITSUBISHI DIGITAL ASSP
M66238FP
STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
REGISTER CONFIGURATION 1. Clock frequency setting command Reference clock generation 12-bit division ratio, PLL syntheData bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
sizer 15-bit division ratio and CKO/PLLO division ratio are set at address (A1, A0) = (0, 0).
Description Default 0 1 0
12-bit reference clock dividing ratio is set. D11 and D0 correspond to MSB and LSB, respectively.
1 0
K = (Dk x 2k)
k=0
11
0 0 0
K: Reference clock dividing ratio
1 0 0 0 0 0 0 1 0
15-bit PLL synthesizer dividing ratio is set. D26 and D12 correspond to MSB and LSB, respectively.
1 1
N = (Dn x 2n-12)
n = 12
26
1 1 1
N: PLL synthesizer dividing ratio
0 0 0 0 0
Setting of CKO/PLLO dividing ratios
Dividing ratio 1/1 1/2 1/4 1/8 1/16 1/32 D29 0 0 0 0 1 1 D28 0 0 1 1 0 0 D27 0 1 0 1 0 1 PLLO/CKO oscillator frequency 25MHz ~ 50MHz 12.5MHz ~ 25MHz 6.25MHz ~ 12.5MHz 3.125MHz ~ 6.25MHz 1.563MHz ~ 3.125MHz 0.781MHz ~ 1.563MHz Remarks
0 1 0
3
MITSUBISHI DIGITAL ASSP
M66238FP
STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
2. Operating mode setting commands Address (A1, A0) = (1, 0) allows setting of one-shot pulse polarity and width, trigger edge, M66238 entire halt, charge
pump and VCO halt, phase comparator UP/DOWN output, LPF cutoff, CKO/PLLO switching, VCO switching and charge pump switching.
Data bit 0 D0 1 0 D1 1 D2 D3 0 1 0 1 0 D4 1 0 D5 1 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 ************* In normal use: "0" set 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Setting of trigger edge D1 D0 0 0 1 1 0 1 0 1
Description Description CKO is stopped when TR="H". CKO is stopped when TR="L". CKO is output when TR="H". CKO is output when TR="L".
Default 0
Synchronizes with TR Synchronizes with TR Synchronizes with TR Synchronizes with TR
0
When trigger occurs: spike of sync clock is not eliminated. When trigger occurs: spike of sync clock is eliminated (disabled when D1=1). Polarity of one-shot pulse: Negative pulse Polarity of one-shot pulse: Positive pulse Setting of one-shot pulse width D5 D4 Description 0 0 CKO 2-cycle width 0 1 CKO 4-cycle width 1 0 CKO 8-cycle width 1 1 CKO 16-cycle width CKO/PLLO pin: CKO output CKO/PLLO pin: PLLO output Entire M66238: Operating state Entire M66238: Halt state VCO: Operating state VCO: Halt state Charge pump: ON Charge pump: OFF Low pass filter: Operating state Low pass filter: Separated Normal use: Not output to outside Phase comparator UP/DOWN output enable Normal use VCO test circuit set Normal use Charge pump test circuit set Normal use 15-bit counter test clock enable Normal use Sync clock generator test clock enable Normal use Sync clock generator test input enable Normal use 12-bit counter test output enable Normal use 15-bit counter test output enable Normal use Sync clock generator trigger test output enable Normal use Sync clock generator test output enable
0 0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ************* 0
D29
4
MITSUBISHI DIGITAL ASSP
M66238FP
STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
3. Dummy trigger generating command The internal status of sync clock generator becomes unstable and a stable sync clock output (CKO) is not obtained after the power is turned on, after a reset is cleared or after an internal VCO oscillator frequency is set. To obtain a stable sync clock output, enter a trigger signal from the TR input afData bit 0 D0 1 D1 - - - - - - - - - - - - - - - -> D29 0 1 0 1
ter VCO oscillator becomes stable, or enter a dummy trigger generating command from the MCU. The PLL synthesizer oscillator frequency after the cancellation of a reset depends on a default (See the register configuration). Set the command for address (A1, A0) = (1, 1).
Description Default
The command must be stored two times continuously when a dummy trigger is generated. For the first time, set the dummy trigger generating command with D0=1. For the second time, set the dummy trigger generating command with D0=0. The second setting becomes a sync edge and a clock begins to be output from CKO. After the first setting, CKO is in the halt state.
0
0 - - - - - - - - - - - - - - - - - - ->
In normal use: "0"
0
5
MITSUBISHI DIGITAL ASSP
M66238FP
STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
OPERATING TIMING 1. Sync clock spike non-removal mode upon occurrence of trigger 1-1 Setting of trigger edge when D1=0 One-shot pulse start timing: 1st leading edge of CKO after TR fall One-shot pulse polarity: Negative pulse One-shot pulse width: 16 cycles of CKO
tp=1/fvco Internal VCO oscillator clock tw(TR) tlp
CKO output dividing ratio: 1/2 division An example set for the condition of address (A1, A0)=(1, 0), data (D6, D5, D4, D3, D2, D1, D0)=(0, 1, 1, 0, 0, 0, 0) is shown below. CKO is a clock output synchronized by TR and PULSE is a one-shot pulse synchronized with the rise of CKO.
TR tsp(CKO) tss(CKO) CKO SPIKE PULSE tss(PULSE) t tp=1/fout t
tw(PULSE)
1-2 Setting of trigger edge when D1=1 One-shot pulse start timing: 1st leading edge of CKO after TR rise (except the rise of a spike which occurs when CKO is stopped). One-shot pulse polarity: Negative pulse One-shot pulse width: 16 cycles of CKO
CKO output dividing ratio: 1/2 division An example set for the condition of address (A1, A0)=(1, 0), data (D6, D5, D4, D3, D2, D1, D0)=(0, 1, 1, 0, 0, 1, 0) is shown below. CKO is a clock output synchronized by TR and PULSE is a one-shot pulse synchronized with the rise of CKO.
tp=1/fvco Internal VCO oscillator clock tw(TR)
tlp
TR tsp(CKO) t tss(CKO) CKO t SPIKE PULSE tp=1/fout
tw(PULSE)
6
MITSUBISHI DIGITAL ASSP
M66238FP
STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
2. Sync clock spike removal mode upon occurrence of trigger When address (A1, A0)=(1, 0) and data (D6, D5, D4, D3, D2, D1, D0)=(0, 1, 1, 0, 1, 0, 0), CKO with the first rise after occurrence of a trigger is output and then CKO stops.
However, this mode is not available when D1=1 in trigger edge setting. Set a wide TR so that TR sync edge is entered 200ns or more after CKO stops.
tw(TR)
TR 200ns or more required t tss(CKO) 1st t tss(CKOB) t PULSE tss(PULSE)
CKO
CKOB
tw(PULSE)
1) 200ns or more required 2) Note: tss (CKO, CKOB, PULSE) is defined by input clock width "L" + . In addition, the value of denotes IC internal delay, and the values of and tss are definite unless temperature, Vcc, etc. are changed, and tss variations at that time is defined as t (sync accuracy: jitter).
CKO/PLLO output frequency range The M66238 requires an internal VCO oscillator frequency of 25MHz to 50MHz. Settings of dividing ratio K of 12-bit divider and dividing ratio N of 15-bit counter are required in order to determine the internal VCO oscillator frequency. The relation between the settings and the internal VCO oscillator frequency is shown below. fin x N (MHz) K
Oscillator frequency
fVCO =
11
K= (Dk x 2k)
k=0 26
N= (Dn x 2n-12)
n = 12
3) Note: Setting of fin/K100kHz is recommended in consideration of the frequency accuracy characteristics of PLL output. Therefore, set the division ratio K of the 12 bit divider and the division ratio N of the 15 bit counter to meet the following conditions: 25MHzfvco50MHz In addition, for PLLO and CKO, setting the division ratios of the sync/division circuit (synchronous clock generating area) to 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 will allow the frequencies of 0.78Hz - 50MHz to be accommodated.
7
MITSUBISHI DIGITAL ASSP
M66238FP
STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc Vi Vo Pd Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Storage temperature Conditions Ratings -0.5 ~ +7.0 -0.5 ~ VCC + 0.5 -0.5 ~ VCC + 0.5 650 -65 ~ 150 Unit V V V mW C
When board is mounted
Remarks: All voltages adopt the GND pin of the circuit as the base (0V) and absolute values are displayed for maximum and minimum values.
RECOMMENDED OPERATING CONDITIONS (Ta=0 to 70C)
Symbol Vcc GND Vi Vo Topr Parameter Supply voltage Supply voltage Input voltage Output voltage Operating ambient temperature Min. 4.75 0 0 0 Limits Typ. 5 0 Max. 5.25 VCC VCC 70 Unit V V V V C
Remarks: The direction of current flowing into a circuit is defined to be positive (no sign) and the direction of current flowing out is defined to be negative (- sign). Absolute values are displayed for maximum and minimum values.
ELECTRICAL CHARACTERISTICS (Ta=0 to 70C, Vcc=5V5%, GND=0V)
Symbol VIH VIL VIH VIL VOH VOL ICC(S) ICC(a) IIH IIL CI Parameter High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Supply current (at time of standstill) Supply current (at time of operation) High-level input current Low-level input current Input capacitance TR XIN GND=0V, IOH=-4mA GND=0V, IOL=4mA GND=0V, Vl=Vcc or GND GND=0V, CKO=50MHz Vl=Vcc or GND GND=0V, VI=VCC GND=0V, VI=0V Conditions Min. 2 0.8!VCC 0.2!VCC VCC-0.8 0.55 50 120 10 -10 10 Limits Typ. Max. 0.8 Unit V V V V V V A mA A A pF (Note) Measurement circuit
Remarks: The direction of current flowing to the circuit is specified to be positive (no sign).
8
MITSUBISHI DIGITAL ASSP
M66238FP
STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
TIMING REQUIREMENTS (Ta=0 to 70C, Vcc=5V5%, GND=0V)
Symbol tw(CS) tsu(CS-SCK) th(SCK-CS) tw(SCK) tsu(SIN-SCK) th(SCK-SIN) fin fiDUTY tw(TR) tr tf Parameter CS width CS set up time CS hold time SCK width SIN set up time SIN hold time Clock input frequency Clock input duty Trigger input "H" pulse width Clock input rising time Clock input falling time Conditions Min. 1 50 50 25 25 25 7 40 200 Limits Typ. Max. Unit s ns ns ns ns ns MHz % ns ns ns
12 60 5 5
SWITCHING CHARACTERISTICS (Ta=0 to 70C, Vcc=5V5%, GND=0V)
Symbol fvco fout t tss(CKO) tss(CKOB) tss(PULSE) tsp(CKO) tsp(CKOB) tw(PULSE) foDUTY(CKO) foDUT(CKOB) Parameter VCO oscillation frequency Synchronous output frequency Synchronous accuracy (jitter) Synchronous clock output start Synchronous clock reversible output start One-shot pulse output start Synchronous clock output stop Synchronous clock reversible output stop One-shot pulse output width Synchronous clock output duty Synchronous clock reversible output duty Conditions CL=15pF Min. 25 Limits Typ. Max. 50 50 3 tlp+200 tlp+200 tlp+200 40 40 n * tp+10 60 60 Unit MHz MHz ns ns ns ns ns ns ns % %
n * tp-10 40 40
(Notes) * tp=1/fout, tlp=tp ! (100 - fvcoduty)/100 * The n value of one-shot pulse output width is set in the register.
MEASUREMENT CIRCUIT
Input
VCC
Output
PG
Tested element ZO CL
* Waveform for switching test Input pulse level XIN: 0 to Vcc, TR: 0 to 3V Input pulse rising time: 3 ns Input pulse falling time: 3 ns Zo: 50 Decision voltage Input voltage XIN: Vcc/2, Tr: 1.3V Output voltage All outputs: Vcc/2 * Electrostatic capacitance: CL includes floating capacitance of connection and probe input capacitance.
9
MITSUBISHI DIGITAL ASSP
M66238FP
STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
INPUT TIMING
(1) Register setting
CS 50% tsu(CS-SCK) tw(SCK) SCK 50% tsu(SIN-SCK) SIN 50% 50% 50% tw(SCK) th(SCK-CS) VCC 0V tw(CS) VCC 0V
th(SCK-SIN) VCC 50% 0V
(2) Clock from trigger input and one-shot pulse output
3V TR 1.3V 0V
CKO CKOB PULSE 50%
VOH
VOL
tss
(3) Stop of clock from trigger input
3V TR 1.3V 0V
CKO CKOB 50%
VOH
VOL
tsp
(4) Trigger input width
3.0V TR 1.3V 1.3V 0V tw(TR)
(5) One-shot pulse width
VOH PULSE 50% 50% VOL tw(PULSE)
10
MITSUBISHI DIGITAL ASSP
M66238FP
STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
APPLICATION CIRCUIT EXAMPLE
Digital power supply 1 2 Programmable Interface 3 4 5 6 32 31 30 29 28 27 7.5k 2k 1.2k 0.015F Analog GND 24 23 22 21 NC 20 NC 19 18 17 Programmable Interface Analog power supply
M66238FP
7 8 1M 9 10 Crystal oscillator 30pF 30pF NC 11 12 13 14 15 16
26 25
Digital GND
11

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